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CDB4353
1. CDB4353 SYSTEM OVERVIEW
The CDB4353 evaluation board is an excellent means of quickly evaluating the CS4353. The CS8416 digital audio
interface receiver provides an easy interface to digital audio signal sources, including the majority of digital audio
test equipment. The evaluation board also allows the user to supply external PCM clocks and data through two sep-
arate header options for system development. Configuration of the CDB4353 can be modified through piano switch
S1, see Table 4 . The CDB4353 system block diagram and signal flow is shown in Figure 31 , and the CDB4353
schematics are shown in Figures 32 and 33 .
2. CS4353 DIGITAL-to-ANALOG CONVERTER
A description of the CS4353 is included in the CS4353 datasheet.
3. CS8416 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8416 Digital Audio Receiver,
Figure 32 . The outputs of the CS8416 include a serial bit clock, serial data, left-right clock, and a 128/256 Fs master
clock. The operation of the CS8416 and a discussion of the digital audio interface is included in the CS8416
datasheet.
The evaluation board has been designed such that the input can be either optical or coaxial, see Figure 32 . How-
ever, both inputs cannot be driven simultaneously.
Position 3 of piano switch S1 sets the CS8416 output data format to either I2S (down) or LJ (up). Position 2 of S1
sets the output MCLK to LRCK ratio of the CS8416. This switch should be set to 256 (down) for input Fs<=48 kHz
and can be either 256 (down) or 128 (up) for Fs>48 kHz. The CS8416 must be manually reset via S2 after either
switch has been toggled for the change to take effect.
4. INPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow interfacing to external systems via headers J13 and J4. Header
J13 allows the evaluation board to accept externally generated PCM clocks and data at a nominal voltage of 3.3 V.
The PCM clocks and data are buffered, level-shifted to the VL supply, and then input to the CS4353. The schematic
for the clock/data input is shown in Figure 33 . Position 1 of S1 selects the CS4353 PCM source as either the CS8416
(up) or header J13 (down).
Note:
If the VL supply is set to a low voltage level (VL<1.8 V), termination resistors may need to be added to the
J13 header signals to match the source and transmission-line impedances that are driving the header. This
may be accomplished by soldering resistors across the rows of J13 on the back of the evaluation board.
Header J4 bypasses position 1 of S1 and allows for a direct connection of PCM clocks and data to the CS4353.
Under normal operation, shunts placed across the left two rows of J4 connects the PCM clocks and data from the
source specified by position 1 of S1 to the CS4353. An external system can be directly connected to the CS4353 by
removing the shunts on J4 and connecting PCM clocks and data across the right two rows of J4 using a ribbon cable.
A single row of “GND” pins are provided to maintain signal ground integrity. Signals input to header J4 must be at
the same voltage level as the VL supply on the evaluation board. The schematic for the header J4 and CS4353 is
shown in Figure 32 .
Please see the CS4353 datasheet for more information on clocking data into the CS4353.
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DS803DB2
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